8 Commits

Author	SHA1	Message	Date
fawce	dd1056bf30	generator backed component, and a starter test for a source.	2012-08-01 23:41:44 -04:00
fawce	318065125f	refactored component to use a generator	2012-08-01 21:43:15 -04:00
fawce	9deaefe6e6	fixes for tests	2012-07-30 13:52:38 -04:00
fawce	abf9c8efa5	exception handling code revised. gevent, pypy, and threadsim vestiges removed. ... devel flag removed.	2012-07-26 16:22:13 -04:00
fawce	dd8c84b0db	added stack trace to exception message, wrapped it in BT UPDATE FRAME	2012-07-25 14:40:14 -04:00
fawce	c02d15016a	added timeouts for component when waiting to hear from the monitor. proof of concept exception relay for algorithm's initialize method.	2012-07-24 23:43:40 -04:00
fawce	d950973f0d	added a proc join to ensure we block on the simulation fully exiting all processes.	2012-07-24 17:43:49 -04:00
fawce	ad10f2aa85	fixed up tests to abandon thread simulator.	2012-07-24 16:43:02 -04:00