 Li, Jiang
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0b952af458
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[Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257)
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2024-09-11 09:46:46 -07:00 |
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Lucas Wilkinson
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a8d604ca2a
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[Misc] Disambiguate quantized types via a new ScalarType (#6396)
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2024-08-02 13:51:58 -07:00 |
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Li, Jiang
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3bbb4936dc
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation (#6125)
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2024-07-26 13:50:10 -07:00 |
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Chip Kerchner
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38a1674abb
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Support CPU inference with VSX PowerPC ISA (#5652)
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2024-06-26 21:53:04 +00:00 |
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Jie Fu (傅杰)
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ab66536dbf
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[CI/BUILD] Support non-AVX512 vLLM building and testing (#5574)
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2024-06-17 14:36:10 -04:00 |
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Jie Fu (傅杰)
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cd9c0d65d9
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[Hardware][Intel] Support CPU inference with AVX2 ISA (#5452)
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2024-06-13 17:22:24 -06:00 |
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bnellnm
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5467ac3196
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[Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047)
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2024-06-09 16:23:30 -04:00 |
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0e3f06fe9c
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[Hardware][Intel] Add CPU inference backend (#3634)
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Yuan Zhou <yuan.zhou@intel.com>
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2024-04-01 22:07:30 -07:00 |
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