7 Commits

Include renames

Author	SHA1	Message	Date
3 people	73202dbe77	[Kernel][Misc] register ops to prevent graph breaks (#6917) ... Co-authored-by: Sage Moore <sage@neuralmagic.com>	2024-09-11 12:52:19 -07:00
Li, JiangandGitHub	0b952af458	[Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257)	2024-09-11 09:46:46 -07:00
Lucas WilkinsonandGitHub	a8d604ca2a	[Misc] Disambiguate quantized types via a new ScalarType (#6396)	2024-08-02 13:51:58 -07:00
Li, JiangandGitHub	3bbb4936dc	[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation (#6125)	2024-07-26 13:50:10 -07:00
Michael GoinandGitHub	978aed5300	[Kernel][Attention] Separate Attention.kv_scale into k_scale and v_scale (#6081)	2024-07-16 15:31:32 -07:00
Roger WangandGitHub	bd620b01fb	[Kernel][CPU] Add Quick gelu to CPU (#5717)	2024-06-21 06:39:40 +00:00
bnellnmandGitHub	5467ac3196	[Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047)	2024-06-09 16:23:30 -04:00