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Fixing bug in write out.

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GudniRos
2016-04-08 09:40:26 -07:00
parent 083742cb40
commit 90b0301408
1 changed files with 1 additions and 1 deletions
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SimPEG/Directives.py
+1 -1
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@@ -222,7 +222,7 @@ class SaveOutputDictEveryIteration(_SaveEveryIteration):
mref = 0
mx = self.reg.Wx * ( self.reg.mapping * (self.invProb.curModel - mref) )
phi_mx = 0.5 * mx.dot(mx)
if self.prob.mesh.dim < 2:
if self.prob.mesh.dim >= 2:
my = self.reg.Wy * ( self.reg.mapping * (self.invProb.curModel - mref) )
phi_my = 0.5 * my.dot(my)
else: