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Merge branch 'master' into parallel
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@@ -119,8 +119,6 @@ class BaseSrc(object):
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rxList = None #: SimPEG Receiver List
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rxPair = BaseRx
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knownSrcTypes = None #: Set this to a list of strings to ensure that srcType is known
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def __init__(self, loc, srcType, rxList, **kwargs):
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assert type(rxList) is list, 'rxList must be a list'
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for rx in rxList:
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@@ -132,16 +130,6 @@ class BaseSrc(object):
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self.rxList = rxList
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Utils.setKwargs(self, **kwargs)
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@property
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def srcType(self):
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"""Source Type"""
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return getattr(self, '_srcType', None)
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@srcType.setter
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def srcType(self, value):
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known = self.knownSrcTypes
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if known is not None:
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assert value in known, "srcType must be in ['%s']" % ("', '".join(known))
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self._srcType = value
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@property
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def nD(self):
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