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59c2216ec05da0750633241e3727db74d24ff101
remove SrcType, put rx list first in inputs for src
simpegdc
A DC resistivity forward modelling and inversion package for SimPEG.
Documentation: http://simpeg-dc.readthedocs.org/en/latest/
Code: https://github.com/simpeg/simpegdc
Tests: https://travis-ci.org/simpeg/simpegdc
Bugs & Issues: https://github.com/simpeg/simpegdc/issues
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Python
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Cython
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