wassname/simpeg

mirror of https://github.com/wassname/simpeg.git synced 2026-07-03 21:14:16 +08:00

T

rowanc1 f23eb17d78 break out WennerArray into a few pieces

2014-07-12 12:57:18 -05:00

Update travis

2014-01-24 11:21:06 -07:00

break out WennerArray into a few pieces

2014-07-12 12:57:18 -05:00

.coveragerc

Major updates.

2014-07-03 13:25:16 -07:00

.gitignore

Merge branch 'DCproblem' of https://github.com/simpeg/simpeg

2014-01-24 10:58:57 -07:00

.travis.yml

Major updates.

2014-07-03 13:25:16 -07:00

LICENSE

Merge branch 'DCproblem' of https://github.com/simpeg/simpeg

2014-01-24 10:58:57 -07:00

README.md

add coverage to readme

2014-07-03 13:45:53 -07:00

requirements.txt

added matplotlib to the requirements

2013-11-26 18:07:19 -08:00

setup.py

Setup.py

2014-02-05 13:54:39 -08:00

README.md

simpegdc

A DC resistivity forward modelling and inversion package for SimPEG.

Documentation: http://simpeg-dc.readthedocs.org/en/latest/

Code: https://github.com/simpeg/simpegdc

Tests: https://travis-ci.org/simpeg/simpegdc

Build Status:

Coverage Status:

Bugs & Issues: https://github.com/simpeg/simpegdc/issues